macro_gen
Dev Log #2: Sizing Combinational Logic by Logical Effort2026-09-29
macro_gen now sizes arbitrary combinational CMOS logic by logical
effort, relative to the inverter characterized in part 1, and buffers
outputs to log4(F) stages. Method with a fully worked example,
calibration of the model constants, and a comparison against SPICE on
eleven SKY130 benchmarks.