Blog

macro_gen now sizes arbitrary combinational CMOS logic by logical effort, relative to the inverter characterized in part 1, and buffers outputs to log4(F) stages. Method with a fully worked example, calibration of the model constants, and a comparison against SPICE on eleven SKY130 benchmarks.

Part 1 of an ongoing series on macro_gen, an automated cell-characterization tool. Why automate this space, how today’s sizing loop actually works in Rust, real ngspice results from varying Vinv, and where evolutionary search, game theory, and GNNs come in next.

How to shift verification, exploration, and design entry left, catching bugs at spec time instead of silicon time.

From the formal theory of scheduling in architectural synthesis to a production bug where an O(n²) ILP solver consumed 64 GB and 15 hours on 10,000 BVI signals.

A deep dive into IP-XACT, exploring its role in modern SoC design and why it’s both loved and feared by engineers.