skywater-130

• macro_gen Dev Log #2: Sizing Combinational Logic by Logical Effort 2026-09-29
  macro_gen now sizes arbitrary combinational CMOS logic by logical effort, relative to the inverter characterized in part 1, and buffers outputs to log4(F) stages. Method with a fully worked example, calibration of the model constants, and a comparison against SPICE on eleven SKY130 benchmarks.
• macro_gen Dev Log #1: Teaching a Computer to Size an Inverter, Honestly 2026-09-20
  Part 1 of an ongoing series on macro_gen, an automated cell-characterization tool. Why automate this space, how today’s sizing loop actually works in Rust, real ngspice results from varying Vinv, and where evolutionary search, game theory, and GNNs come in next.